1. Field of the Invention
The present invention relates to a multi-user receiving apparatus for use in a base station with which a plurality of mobile stations each assigned to a respective use simultaneously communicate in accordance with a single-carrier frequency division multiple access scheme.
2. Description of the Related Art
In an uplink radio system for next-generation mobile communication packet access, importance is attached to a high transmission power efficiency of terminals, and radio transmissions free of interference between users who simultaneously make accesses, in order to expand communication areas. As a radio scheme that satisfies these requirements, a frequency division multiple access (FDMA) scheme which employs a single carrier (SC) having a low peak to average power ratio (PAPR), has been under consideration. The SC-FDMA scheme divides a frequency band of a system into sub-bands, each of which is utilized by multiple users. Each user performs a single carrier transmission having a band that is variable in accordance with a required transmission rate. A feature of the SC-FDMA scheme is that each of the user signals is not subjected to interference because of their different carrier frequencies, and the scheme is therefore suitable for packet transmissions which are difficult to apply a highly accurate transmission power control, as compared with a code division multiple access (CDMA) and the like. FIG. 1 shows a frequency spectrum of a SC-FDMA signal when three users U1, U2, U3, for example, make simultaneous accesses.
FIG. 3 illustrates a block diagram of a conventional, typical receiving apparatus for SC-FDMA signals. The conventional SC-FDMA signal receiving apparatus comprises K (where K is an integer not less than one) user receivers 101-k (where 1≦k≦K), each being associated with respective users. Each user receiver 101-k converts the frequency of an SC-FDMA received signal, and filters and demodulates the frequency-converted SC-FDMA signal. Each user receiver 101-k is comprised of frequency converter 102, reception filter 103, and demodulator 104. Frequency converter 102 is supplied with a SC-FDMA received signal, and converts the carrier of each user signal to a zero frequency. Reception filter 103 limits the band of each user signal to separate the user signal and suppress noise. As reception filter 103, a raised cosine roll-off filter is typically used. Demodulator 104 performs such processing as timing detection, transmission channel estimation and equalization, and outputs a demodulated signal. A variety of methods may be employed to demodulate a single-carrier signal. For example, consideration is given to using a frequency domain equalizer which can significantly reduce the amount of processing, by performing multi-path equalization through frequency-domain signal processing (D. Falconer, S. L. Ariyavisitakul, A. Benyamin-Seeyar, and B. Didson, “Frequency Domain Equalization for Single-Carrier Broadband Wireless Systems,” IEEE Comun. Mag., vol. 40, no. 4, pp. 58-66, April 2002.).
FIG. 2 shows an exemplary format for a packet signal when a frequency domain equalizer is used. The packet signal is made up of a plurality of blocks, each of which contains a pilot or data. In the illustrated example, the first block contains a pilot signal, followed by a plurality of sequential blocks each containing a data signal. A guard interval (GI) is provided at the beginning of each block in order to avoid multi-path interference from a previous block during DFT (Discrete Fourier Transform) processing. As the GI, a cyclic prefix is typically used which adds the last data in each block to the top thereof.
Demodulator 104 comprises delay profile generator 105, timing detector 106, transmission channel estimator 107, serial/parallel (S/P) converter 108, DFT unit 109, weight calculation unit 110, guard interval (GI) remover 111, S/P converter 112, DFT unit 113, equalizing filter 114, inverse discrete Fourier transform (IDFT) unit 115, and parallel/serial (P/S) converter 116. Delay profile generator 105 receives a signal, the band of which has been limited by reception filter 103, and generates a delay profile based on a detected sliding correlation of a pilot signal multiplexed on the received signal to a known pilot code. Timing detector 106 receives the delay profile generated by delay profile generator 105, and detects timings of a plurality of paths, at higher levels, including a timing of the first path. The timing of the first path is used for controlling a DFT timing, and the timing of other paths is used for estimating each transmission channel. Transmission channel estimator 107 is supplied with the received signal, the band of which has been limited by reception filter 103, and with path timings detected by timing detector 106. Transmission channel estimator 107 then estimates a transmission channel estimate for each path using a pilot signal included in the received signal S/P converter 108 performs a serial to parallel conversion of a transmission channel response sequence that is an alignment of the transmission channel estimates for respective paths on a time axis. DFT unit 109 receives the transmission channel response sequence converted by S/P converter 108, and outputs a transmission channel estimate converted into a frequency domain. Weight calculation unit 110 receives the transmission channel estimate output from DFT unit 109, and calculates weight for an equalizing filter in accordance with a minimum mean square error (MMSE) method, a zero forcing method or the like. GI remover 111 is supplied with the received signal, the band of which has been limited by reception filter 103, and with the DFT timings detected by timing detector 016, and GI remover 111 removes a portion of the received signal corresponding to GI. S/P converter 112 performs a serial to parallel conversion of the received signal, from which the GI has been removed by GI remover 111. DFT unit 113 receives the received signal converted by S/P converter 112, and converts the received signal into a frequency domain. Equalizing filter 114 receives the received signal, which has been converted into the frequency domain, and the equalization weight calculated by weight calculation unit 110, and multiplies the received signal by the equalization weight for each sub-carrier to equalize the received signal. IDFT unit 115 receives the equalized signal in the frequency domain output from equalizing filter 114, and performs IDFT on the equalized signal for conversion into a time domain. P/S converter 116 performs a parallel to serial conversion of the equalized signal converted into the time domain to generate a demodulated signal.
The conventional SC-FDMA signal receiving apparatus shown in FIG. 3 is problematic in that processing in frequency converter 102 and processing in reception filter 103 which is required to accomplish a variable bandwidth are made complicated by the increase of users. Additionally, the method of performing timing detection and transmission channel estimation using a detected correlation with pilot codes in the time domain is problematic in that it requires a large amount of processing, and the reception characteristics are degraded due to the influence of multi-path interference.